(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes related to the deposition of spin-on organic and silicaceous polymeric materials to form dielectric layers on semiconductor wafers.
(2) Background to the Invention and Description of Previous Art
Integrated circuits(ICs) are manufactured by first forming discrete semiconductor devices within the surface of silicon wafers. A multi-level metallurgical interconnection network is then formed over the devices, contacting their active elements and wiring them together to create the desired circuits. The wiring layers are formed by depositing an insulating layer over the discrete devices, patterning and etching contact openings into this layer, and then depositing conductive material into these openings. A conductive layer is then applied over the insulating layer and is patterned to form wiring interconnections between the devices, thereby creating a level of basic circuitry. The basic circuits are then further interconnected by utilizing additional wiring levels laid out over additional insulating layers with via pass throughs.
Spin on coatings have been used in integrated circuit manufacturing for many years. These materials can be applied in liquid form and subsequently hardened or cured to form solid or semi solid layers. The most familiar spin on materials are photoresists and polyimides which have been used since the early 1970s. The photoresists, of course, are generally used for patterning only and as such, are transient films and do not remain in the finished product. Polyimide films have been used from time to time as dielectric and filler layers but frequently suffer processing incompatibilities such as severe outgassing, thermal instability and deformation by shrinkage. More recently, spin-on glasses(SOGs) have received widespread use and success in wafer surface planarization but have also been plagued by outgassing causing blistering and corrosion problems.
Each time a layer of metallization is formed on an integrated circuit wafer and circuit paths are etched within it, the metal pattern introduces a non-planar surface. When the next insulative layer is deposited, by conformal methods such as CVD (chemical vapor deposition), the irregular surface topology is replicated at the insulative layer surface. In order to prevent the cumulative replication of subjacent metal pattern topologies throughout the various metallization levels, it has become common practice in multi-level integrated circuit manufacturing to include means for planarizing the each insulative layer prior to deposition of a metallization layer.
One method for achieving such planarization entails the deposition of an SOG in a liquid form, for example a liquid monomer which, when spun onto the wafer surface, flows into the topological contours. After deposition, the material is dried and cured to form a polymeric insulative film with a smooth, essentially planar, surface for deposition of a subsequent metal layer. The SOGs consist of alcohol soluble silicates and siloxanes which can attain the properties of inorganic glasses when properly cured. The SOGs have found wide acceptance in recent sub-micron semiconductor processing technology because of their low defect density, simplified processing, and low thermal budget. However, the SOG layers have been generally limited to thicknesses of only a few thousand Angstroms. Thicker layers tend to crack and require longer and more careful curing times. A common method of usage is to first deposit a layer of PECVD(plasma enhanced CVD) silicon oxide over a layer of patterned metallization and then lay the SOG over it. The SOG fills in the narrow features. It is then etched back by anisotropic etching to the PECVD oxide surface. The result is the original PECVD layer with the small spacings filled with SOG.
The SOG is deposited by a nozzle directed at the center of a rapidly spinning wafer. Centrifugal force distributes the liquid over the wafer. Excess liquid is flung from the edge of the wafer. The apparatus used to perform this task is of the same type that is conventionally used to deposit photoresist. The wafer is then allowed to dry and then the SOG is cured, typically by a sequence of hot plate steps. The curing process is difficult in that it requires a delicate balance between the rate of solvent and polymerization by-product removal and the rate of formation of the polymer. Failure to provide the proper balance results in cracking and inclusion of impurities which can cause subsequent metal corrosion.
More recently, in order to further improve device performance, researchers have sought to apply insulative materials with lower dielectric constants than the conventional CVD deposited silicate glasses such as silicon oxide, PSG(phosphosilicate glass) and BPSG(borophosphosilicate glass). Various organic insulators such as parylene, fluorinated polyimides and arylene ether polymers, have been successfully used as low dielectric constant(low-k) replacements for silicon oxide. Porous silica based materials such as siloxanes, silsesquioxanes, aerogels, and xerogels have also been implemented as ILD(inter layer dielectric) and IMD(inter-metal dielectric) layers. These materials, like the earlier SOGs used for planarization, are applied by spin on techniques, dried, and cured. Not only do these materials provide a means for planarization but, by virtue of their lower dielectric constant, they also provide a lower capacitance between adjacent conductors thereby improving device performance.
The spin on dielectric (SOD) materials, like the SOGs and polyimides are extremely sensitive to the methods and conditions by which they are dried and cured after application. Not only are the resultant electrical characteristics of the dielectric layer affected by the drying and curing regimen, but also the physical properties including stress, mechanical strength and physical and chemical durability are affected as well. SODs and SOGs, in particular those of a highly porous structure, rapidly absorb moisture when exposed to atmosphere absorb moisture as well as other ambient gases. Quellet, U.S. Pat. No. 5,457,073 reports a method for in-situ discharge of absorbed moisture from porous inorganic or quasi-inorganic SOGs exposed in via openings by vacuum or inert gas annealing at temperatures below 500.degree. C. followed by sealing off the exposed surfaces by depositing the interconnect material into the openings.
Jeng, U.S. Pat. No. 5,548,159 deposits porous dielectric materials over metal patterns and then etches back to leave the porous material only within the narrow line spacings and adjacent to but not over the metal line segments. A dense dielectric material is then deposited over the wafer which seals off the porous dielectric material. Vias are then formed to the metal line segments wholly within the dense dielectric material so that the porous dielectric is not exposed within the via openings. The porous SODs are dried and cured by baking.
Thermal processes for curing SODs have included long bakes in vertical furnaces for periods as long as 5 to 6 hours. More recent approaches have included e-beam curing. However, because of the slow throughput of the furnace curing and the vacuum requirement of the e-beam processing, these methods are not attractive for integrated circuit manufacturing.
Henkel, et.al., U.S. Pat. No. 4,983,419 cites a method of polymerization and cross linking of linear and branched single chain, non functionalized organosiloxanes by photo curing with pulsed laser radiation to form thin dielectric layers. The organosiloxanes may contain alkyl and aryl groups and may be cyclic but must have no functional groups or photo initiators or photo sensitizers. The photo hardening takes place in an oxygen free atmosphere. The layers are reported to have good dielectric properties but none are cited.
Chakravorty, et. al., U.S. Pat. No. 5,124,238 cites a method for curing photo sensitive polyimide films with reduced shrinkage after photo patterning the film with ultraviolet (uv) radiation. A first low temperature bake, prior to the radiation exposure brings about the greatest film shrinkage, due to solvent release. The uv radiation, which causes the cross linking of the polymer, then imparts little additional shrinkage.